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PATTERN Cited by 1 source

Vocab pad to kernel boundary

Intent

Avoid a CUDA kernel-selection performance cliff (cuBLAS → CUTLASS fallback with ~3× slowdown on the LM-head layer) by automatically padding user-controlled tensor dimensions — specifically vocabulary size — to a hardware-friendly boundary (multiple of 64) inside the framework, so developers never need to know the low-level constraint.

First canonical wiki reference: sources/2026-02-13-netflix-scaling-llm-post-training-at-netflix.

Problem

LLM training pipelines frequently expand the vocabulary with custom tokens and semantic IDs. This pushes vocab sizes into ranges (e.g. 128003, 50257, 32003) that don't align with the tile-size boundaries CUDA's matmul dispatcher uses to select the fast-path kernel. When the LM-head GEMM (shape [hidden_dim, vocab_size]) hits a misaligned output dimension, the dispatcher falls back to a slower CUTLASS path — tripling the LM-head layer's execution time per Netflix's measurements.

Two anti-patterns:

  1. Developer-responsibility: document the rule "pad your vocab to multiples of 64" — every team forgets; inconsistent throughput; different vocab sizes per team → non-comparable MFU numbers.
  2. Accept the cliff: ~3× LM-head slowdown on workloads that happen to hit a bad vocab size; silent; team discovers it only via MFU debugging.

Neither is acceptable when vocabulary expansion is a first-class workflow (semantic IDs, domain-specific sentinels).

Solution

Framework-level auto-padding. Inside the LLM-post-training framework, detect the user's specified vocabulary size and round it up to the next multiple of the kernel-friendly boundary (64 in Netflix's case). Hide the padded tokens behind a loss-masking convention so gradients don't flow through them.

user_vocab_size = len(tokenizer)          # e.g. 128003
padded_vocab = ceil_to_multiple(64, user_vocab_size)   # 128064
model = build_model(..., vocab_size=padded_vocab)
# padded positions [128003 .. 128063] never receive valid token IDs
# loss is masked to ignore them if they somehow appear

Netflix's framing:

"The framework now automatically pads vocabulary sizes to multiples of 64 so the compiler selects the fast kernel, preserving throughput without requiring developers to know these low-level constraints." (Source: sources/2026-02-13-netflix-scaling-llm-post-training-at-netflix)

Why framework-level is strictly better than developer-level

Concern Developer-level Framework-level
Consistency across teams ❌ Each team chooses or forgets ✅ Every run uses the same rule
MFU comparability ❌ Depends on team discipline ✅ Deterministic
When hardware/kernel boundaries change ❌ N teams update code ✅ One config change in framework
Developer cognitive load ❌ Must know cuBLAS/CUTLASS rules ✅ Just write the training config

Applicability

  • ✅ LLM post-training / pre-training frameworks serving multiple workloads with heterogeneous vocabulary extensions.
  • ✅ Anywhere a user-controlled tensor dimension determines CUDA kernel selection (LM heads, output projections, MoE gating, embedding tables).
  • ❌ Single-workload pipelines where vocab is fixed and known to hit the fast path.
  • ❌ Situations where the padding cost (extra parameters, extra memory) exceeds the kernel-cliff cost.

Generalisation

The principle generalises beyond vocab padding: any tensor dimension controlled by user code that affects CUDA kernel eligibility should be normalised inside the framework. Examples:

  • Attention head count / head dim padded to tensor-core-friendly multiples.
  • MoE expert count rounded to an even number for all-to-all kernel efficiency.
  • Sequence length rounded to block-size multiples for attention kernels.
  • Hidden dimension padded for FlashAttention tile compatibility.

In each case the question is "is this performance cliff something we want every individual team to learn, or is it a framework concern?"

Trade-offs

Benefit Cost
Eliminates a ~3× LM-head slowdown cliff Slightly larger model (extra padded positions)
Consistent MFU across runs Edge cases where padded tokens leak into loss (must be masked)
No developer cognitive load Requires framework to know the kernel boundaries
One fix applies to all users Boundaries may change with new CUDA versions

Known uses

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