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Write endurance (NAND)

Definition

Write endurance of NAND flash is the number of Program/Erase (P/E) cycles a cell can survive before its bit-error-rate (BER) crosses the ECC-correctable threshold. Each write cycle incrementally degrades the tunnel oxide in the floating-gate transistor; beyond the endurance ceiling the cell becomes unreliable.

Endurance decreases as bits-per-cell increase, because more precise voltage discrimination is required. Approximate industry ceilings:

Media P/E cycles
SLC ~100,000
MLC (2-bit) ~10,000
TLC (3-bit) ~3,000-5,000
QLC (4-bit) ~500-1,500

Why this was the QLC blocker

Meta's 2025-03-04 framing:

"QLC flash as a technology has been around since 2009. Adoption has been slow because it has historically operated at lower drive capacity points — less than 32TB. As well, high cost and limited write endurance didn't make it an attractive alternative to TLC in the datacenter."

At 2010s-era drive capacities, QLC's low P/E ceiling meant a mixed workload (say, the standard 3 DWPD / 5-year datacenter spec) would burn through the cells. Shipping QLC to production required the durability gap to close.

Two levers closed the gap

Lever 1: density increases shifted the math. A modern QLC drive has 10-30× more capacity than its 2010s predecessor. The absolute write volume per day stays the same (workloads don't write faster because the drive got larger), but spread over far more cells → per-cell P/E pressure drops.

Lever 2: workload matching. Meta's 2025 stance:

"QLC flash introduced as a tier above HDDs can meet write performance requirements with sufficient headroom in endurance specifications. The workloads being targeted are read-bandwidth-intensive with infrequent as well as comparatively low write bandwidth requirements."

Deploy QLC under read-dominant, low-write-BW workloads whose write volume is well below the cell's P/E budget. Durability is met by definition — the workload doesn't push enough writes to consume the endurance.

The endurance-power composition

The same property that makes QLC a bad fit for high-write workloads makes it a good fit for power-efficiency:

"Since the bulk of power consumption in any NAND flash media comes from writes, we expect our workloads to consume lower power with QLC SSDs."

Write-light workloads → fewer P/E cycles → lower write power → less energy spent per byte served. The endurance story and the power-efficiency story are two sides of the same coin.

Wear-leveling

Endurance is managed at drive / FTL granularity via wear-leveling — the controller distributes logical writes across all physical cells so no cell is exhausted before others. Host-side FTLs (see DirectFlash) give software direct control of wear-leveling policy.

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