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Hardware-aware model architecture

Definition

Hardware-aware model architecture is a model-design discipline where the model's structural choices are deliberately aligned with the underlying hardware's capabilities and limitations — dtype support, memory hierarchy (HBM ↔ SRAM), kernel-launch overhead, Tensor Core shapes, interconnect bandwidth — so that the model's nominal compute translates directly into realised utilisation rather than memory-bandwidth or overhead waste. It is the design-side companion to concepts/hardware-software-codesign (Source: sources/2026-03-31-meta-adaptive-ranking-model-bending-the-inference-scaling-curve).

What "alignment" means in practice

From Meta's framing: "By developing hardware-aware model architectures that align model design with underlying hardware system and silicon's capabilities and limitations, Adaptive Ranking Model significantly improves hardware utilization in heterogeneous hardware environments."

Concrete alignment decisions:

  • Dtype selection — choose layer precisions (FP8 / BF16 / FP16) that hit the fastest Tensor Core paths the accelerator offers. Meta uses selective FP8 for exactly this reason.
  • Matrix shapes tuned for Tensor Core tile sizes — so matmul operations decompose cleanly into hardware-native tiles (typically multiples of 16 / 32 / 128 depending on precision).
  • Operator grouping for kernel fusion — model structure that allows operators sharing inputs to be fused at kernel level, minimising HBM ↔ SRAM traffic.
  • Small-op consolidation — avoiding thousands of tiny kernel launches by consolidating into compute-dense kernels (e.g. Grouped General Matrix Multiply, horizontal fusion).
  • Memory-hierarchy awareness — keeping working sets within SRAM / L2 cache where possible, minimising HBM round-trips.

Meta's outcome: "boosted model FLOPs utilization (MFU) to 35% across multiple hardware types" — a canonical datum extending concepts/model-flops-utilization into the recsys-serving domain.

Why it's harder than it sounds

A hardware-agnostic model architecture is chosen by ML engineers purely for predictive quality. Hardware-awareness adds a second constraint: the architecture must also be efficient on the deployment target. The design cost:

  • Cross-discipline collaboration — ML researchers and GPU systems engineers co-authoring the architecture, not handing off a model to a separate systems team for post-hoc optimisation.
  • Heterogeneous hardware support — when serving spans multiple accelerator types (e.g. NVIDIA + AMD), the architecture must be efficient on all of them, not just the dominant one.
  • Quality-vs-utilisation tradeoffs — some quality-improving choices (irregular shapes, unusual attention patterns) are hardware-hostile. The discipline is negotiating these at design time, not discovering them at deployment time.

Relationship to the inference trilemma

Hardware-aware architecture is the utilisation-side lever in Meta Adaptive Ranking Model's resolution of the inference trilemma:

  • Request-centric architecture shrinks the compute footprint (linear → sub-linear scaling).
  • Hardware-aware architecture ensures that compute footprint is realised efficiently on the hardware (35% MFU).
  • Multi-card sharding decouples scale from single-GPU memory.

Together they cut cost without giving up model complexity.

Distinction from post-hoc model optimisation

Compiler-level optimisations (operator fusion, kernel tuning) are after-the-fact — they try to make a given architecture fast. Hardware-aware architecture is before-the-fact — it shapes the architecture so optimisations can apply and can yield the full hardware capability. The two are complementary: a hardware-aware architecture gives post-hoc tools more to work with.

Canonical industrial instances on the wiki

  • Meta Adaptive Ranking Model (2026-03-31) — this post; canonical recsys instance, 35% MFU across heterogeneous hardware, selective FP8 + Grouped GEMM + horizontal fusion + HBM↔SRAM traffic minimisation named explicitly.
  • Voyage AI token-count batching (2025-12-18) — MFU-vs-token-count profiling and batch sizing to hit the saturation point; a sibling case on the embedding-inference side rather than recsys.

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